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[Embeded-SCM Develop] freerisc8_11.zip

Description: 8位RISC　CPU的VERILOG编程　SOURCECODE
Platform: | Size: 275274 | Author: | Hits:

[TreeView] RISC_CISC

Description: CPU从指令集的特点上可以分为两类：CISC和RISC。我们所熟悉的 Intel 系列CPU就是 CISC 的 CPU 的典型代表。那么，RISC 又是什么呢？RISC是英文Reduced Instruction Set Computer的缩写，汉语意思为\"精简指令系统计算机\"。相对应的CISC就是\"复杂指令系统计算机\"的意思。 　　随着大规模集成电路技术的发展，计算机的硬件成本不断下降，软件成本不断提高，使得指令系统增加了更多更复杂的指令，以提高操作系统的效率。另外，同一系列的新型机对其指令系统只能扩充而不能减去旧型机的任意一条，以达到程序兼容。这样一来，指令系统越来越复杂，有的计算机指令甚至达到数百条。人们就称这种计算机为CISC（Complex Instruction Set Computer）。如IBM公司的大、中型计算机，Intel公司的8086、80286、80386微处理器等。
Platform: | Size: 8074 | Author: grant | Hits:

[Other resource] RiscCPU8

Description: 可综合的VerilogHDL设计实例: ---简化的RISC 8位CPU设计简介---
Platform: | Size: 219377 | Author: hulin | Hits:

[Other resource] RiscCpu

Description: 4位RISC指令CPU源码,需要的朋友可以看看!
Platform: | Size: 9143 | Author: 陈谦 | Hits:

[VHDL-FPGA-Verilog] openfire_core_latest.tar

Description: openfire实现 microblaze机构的cpu代码,RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡-openfire complete microblaze architecture cpu,RISC CPU Verilog sourcecode and documents
Platform: | Size: 37888 | Author: 将 | Hits:

[VHDL-FPGA-Verilog] risc8

Description: 八位简易risccPU，采用verilog描述，FPGA实现-8bit risc CPU
Platform: | Size: 470016 | Author: 于斌 | Hits:

[VHDL-FPGA-Verilog] RISC_CPU

Description: RISC cpu设计，verilog语言，PIC14位指令集-RISC cpu design, verilog language, PIC14-bit instruction set
Platform: | Size: 350208 | Author: liuweijie | Hits:

[matlab] RISC_CPU_matlab

Description: RISC处理器的matlab代码，里面每个模块划分都很细致，是 FPGA设计RISC处理器的重要参考-RISC CPU DESIGN
Platform: | Size: 4096 | Author: 胡兵 | Hits:

[Other] MTP4

Description: 高性能RISC CPU： • 仅需学习35条指令： - 除跳转指令外，所有指令均为单周期指令 • 工作速度: - 振荡器/ 时钟输入为DC-20 MHz - 指令周期为DC -High-Performance RISC CPU: • Only 35 Instructions to Learn: - All single-cycle instructions except branches • Operating Speed:
Platform: | Size: 7168 | Author: zt | Hits:

[VHDL-FPGA-Verilog] cpu3

Description: 简易CPU可执行8条简单指令,如：add,xor,and等-risc cpu
Platform: | Size: 92160 | Author: youyangbiao | Hits:

[VHDL-FPGA-Verilog] risc8_cpu_verilog

Description: 该实例设计的RSIC-CPU总线结构采用数据线（8位）和指令线（12位）独立分离的哈弗结构，把存储寄存器RAM当做寄存器来寻址使用以方便编程。-The example design of RISC-CPU bus architecture uses a data line (8) and command line (12) is separated with the Harvard architecture, the storage register addressing uses RAM as a register to facilitate programming.
Platform: | Size: 625664 | Author: 荣志强 | Hits:

[VHDL-FPGA-Verilog] RISC_cpu

Description: 一款8位的RISC-cpu 源码可在modelsim仿真出波形-An 8-bit RISC-cpu source code in modelsim simulation waveforms
Platform: | Size: 4569088 | Author: 蓝莓汁 | Hits:

[VHDL-FPGA-Verilog] S16C57

Description: 8位RISC CPU 设计IP，包含了文档、代码、仿真环境等-8BIT RISC MCU implemention reference ip,include rtl code,simulation and document
Platform: | Size: 2382848 | Author: zhangbin | Hits:

[SCM] msp430g2553

Description: 德州仪器(TI) MSP430 系列超低功耗微控制器包含多种器件，它们特有面向多种应用的不同外设集。这种架构与 5 种低功耗模式相组合，专为在便携式测量应用中延长电池使用寿命而优化。该器件具有一个强大的16 位RISC CPU，16 位寄存器和有助于获得最大编码效率的常数发生器。数字控制振荡器(DCO) 可在不到1μs 的时间里完 成从低功耗模式至运行模式的唤醒。(The TI (TI) MSP430 family of ultra low power microcontrollers contain a wide variety of devices, which are unique to different peripherals for a wide variety of applications. This architecture and A combination of 5 low power modes optimized for extended battery life in portable measurement applications. The device features a powerful 16 bit RISC CPU, 16 bit registers, and constant generators that help maximize coding efficiency. The digitally controlled oscillator (DCO) can be completed in less than 1 s Wake up from low power mode to run mode.)
Platform: | Size: 1622016 | Author: fengye0133 | Hits:

[Documents] msp430g2755

Description: 德克萨斯仪器MSP430系列超低功耗微控制器由几个设备组成。 针对不同应用程序的不同外设集。的体系结构，结合五低功耗 模式，优化实现延长电池寿命便携式测量应用。该设备具有 强大的16位RISC CPU，16位寄存器，以及有助于提高代码效率的常数生成器。 数字控制振荡器（DCO）允许唤醒从低功耗模式，在不到1μ美国主动模式(The TI (TI) MSP430 family of ultra low power microcontrollers contain a wide variety of devices, which are unique to different peripherals for a wide variety of applications. This architecture and A combination of 5 low power modes optimized for extended battery life in portable measurement applications. The device features a powerful 16 bit RISC CPU, 16 bit registers, and constant generators that help maximize coding efficiency. The digitally controlled oscillator (DCO) can be completed in less than 1 s Wake up from low power mode to run mode.)
Platform: | Size: 1315840 | Author: fengye0133 | Hits:

[VHDL-FPGA-Verilog] minirisc-master

Description: Implementation of the MiniRisc CPU in Verilog!
Platform: | Size: 90112 | Author: loox_dg | Hits:

[VHDL-FPGA-Verilog] risc_spm_v14

Description: 使用Altera CycloneIV 用Verilog语言实现一个精简指令集cpu(Using Altera CycloneIV to implement a streamlined instruction set CPU in Verilog language)
Platform: | Size: 1055744 | Author: LucienJ | Hits:

[Other] cpusim

Description: C++模拟实现单线程CPU运行RISC-V指令集(C++ Simulated Implementation of RISC-V Instruction Set in Single Thread CPU)
Platform: | Size: 4096 | Author: 月韵星影 | Hits:

[Other systems] Faraday Mixed-size Placement Benchmarks [vlsi] [IC]

Description: ICCAD 2004 Faraday Mixed-size Benchmarks with routing information Faraday Corp. recently released three benchmarks, originally intended for comparisons between structured and conventional ASICs. We apply to these benchmarks a standard ASIC design flow to generate five mixed-size designs. Faraday benchmarks include three commonly-used functional blocks: (I) 16-bit DSP, (II) 32-bit RISC CPU and (III) DMA. Other details on these benchmarks such as the EDA Tools used by Faraday, implementation conditions, settings etc. can be found in on the faraday web-site. To minimize the impact of routing on the results of the accounted placement approaches, we avoid clock-tree generation and power routing in our flows. However, both clock-trees and power rails can be built on theses benchmarks. Following is the description of our ASIC flow which we used for generating the mixed-size benchmarks from the original netlists.
Platform: | Size: 7427884 | Author: ahimsafollower@gmail.com | Hits:

[VHDL-FPGA-Verilog] S1 CPU core

Description: S1 Core (codename Sirocco) is an open source hardware microprocessor design developed by Simply RISC. Based on Sun Microsystems' UltraSPARC T1, the S1 Core is licensed under the GNU General Public License, which is the license Sun chose for the OpenSPARC project.
Platform: | Size: 1114206 | Author: xptogudovan | Hits:
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